1. Technical Field of the Invention
The invention relates generally to communication systems; and, more particularly, it relates to communication system in which parallel processing of signal is performed such as in the context of de-serialization and/or serialization.
2. Description of Related Art
Data communication systems have been under continual development for many years. In many communication systems and signal conditioning systems (e.g., including those that employ one or more serial communication links), the incoming data might be de-multiplexed into multiple channels to utilize the advantage of parallel processing at lower frequency of operation. The clocking scheme for each de-multiplexed channel has to start from a predetermined condition and be synchronized such that serial data ordering can be kept unaltered through the demultiplexed multiple channels.
Generally speaking, a serial signal can be de-serialized into a number of parallel signals such that the entirety of the parallel signals includes all of the information within the serial signal. Because of this parallel arrangement, these des-serialized signals can be processed in parallel. This requires the synchronization described above, so that the parallel signals are all processed appropriately. Prior art approaches to performing the generation of the synchronized clock signals to be used for each of the parallel signals have a number of deficiencies.
FIG. 4 illustrates a prior art approach 400 of synchronized clock signal generation for 8 channels. In the prior art approach 400, one can utilize a single phase rotator 413 to generate the clock outputs (i.e., CLK1, and CLK1B) using 4 separate D latches, shown as reference numerals 410, 420, 430, and 440, respectively.
In addition, one very inflexible characteristic of this prior art approach 400 is the duty cycle distortion which inherently results within the output of each channel. Moreover, this prior art approach 400 only works for an 8-channel system where CLK1 is four times the speed of clock signals CLK<0:7> (e.g., shown as CLK<0>, CLK<1>, CLK<2>, and so on up to CLK<7>). This prior art approach 400 also is not modular to any number of channels; more specifically, this prior art approach 400 can only be applied to a system that employs an even number of synchronized clock signals (i.e., it cannot accommodate odd numbers of channels).